Advanced Micro Devices (AMD) is a semiconductor company, known for designing and developing computer processors and graphics technologies. Founded in 1969, the company is based in Santa Clara, Calif., with a significant operation in Austin, Texas.

Business Planning Manager, Cloud

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

The Role

AMD is searching for a Business Planning Manager who will help define and drive our EPYC Datacenter CPU business and strategy. This person will join the Cloud Business Group, a tightly knit team of seasoned and high-output professionals who collectively drive AMD’s Datacenter Strategy and business development activities for the Cloud Segment. The success of the Cloud Group is built on ownership and delivery of results for the rapidly growing server business. The team operates in deep partnership with stakeholders across product, finance, and operations.

The Person

The ideal candidate will possess a breadth of abilities and skills, including CPU product knowledge, strong business operations skills, previous Chief of Staff experience, ability to craft customer facing and executive level presentations, ability to deal with highly ambiguous projects and being able to deliver results on time with little to no supervision. Most importantly, you are the business operations leader, contributing to strategy, setting direction, and achieving success in all facets. You must be self-driven, and capable of operating autonomously.

The applicant must be a team player with a commitment to meeting deadlines and an aptitude to thrive in a fast paced, multi-tasking environment. The position is based in Santa Clara, CA.

• Executive presence and credibility needed to influence senior leadership in a matrixed environment
• Ability to synthesize and convey concepts into proposal, requirements, and action plans
• Exceptional communication skills – both listening and written / verbal – to facilitate alignment with a range of internal stakeholders
• Skill in analyzing tradeoffs and making analytical, fact-based recommendations that have substantial business and financial impacts
• Ability to build relationships with strategic customers and partners to ensure that AMD products meet or exceed the evolving needs of the market
• Collaboration skills to engage a team of operations, finance, and business development professionals to achieve outstanding business results

Key Responsibilities

• Supply & demand management of customer engineering samples
• Customer contract management & internal contracts process management
• Management & subject matter expert of internal business operations tools
• Executive level content creation & design incl. Business Unit All Hands meetings, customer presentations, monthly leadership reports, quarterly business unit reports
• Drive implementation of strategic initiatives across the server business unit in partnership with the business unit teams

Preferred Experience

• Five or more years with a combination of driving business operations/ planning and prior Chief of Staff experience
• Understanding of financial treatment for various business deal structures
• Experience in working with legal contracts (creation, reviews, negotiations)

Academic Credentials

Bachelor or Master in related field with MBA being highly desired

Silicon Design Engineer

As a member of the Graphics Technologies and Engineering (G&E) Methodology and Technology team, you will develop and improve design flows bringing to life cutting-edge designs in latest technologies. You will work closely with the Block level Physical Design, Full Chip Floorplan / Netlist,  Full Chip Static Timing Analysis, CAD, Methodology and Technology Teams to achieve first pass silicon success.

Key Responsiblities

• Physical design and timing methodology development on a particular nodes and SOCs
• Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environment for an SOC
• Full chip / sub-system/ Tile level timing analysis with bleeding edge STA methodologies
• Full chip / sub system level Clock tree synthesis and advanced clock tree construction and analysis.
• Understand design requirements, timelines and various milestones of a project
• Block and top level Formal verification, Signoff
• Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion, IRdrop and logic equivalence
• Statistical and Static Timing Analysis, Variation aware analysis, stdcell Library characterization enhancements
• Developing and Integrating ML and LLM applications for Physical Design and Analysis flows
• Collaborate with CAD and EDA vendors to further strengthen AMD timing closure
• Performing data analysis and identifying design trends
• Customizing and implementing solutions for new challenges
• Collaborating with multi-site engineering teams to reach project goals
• Hands-on in reference flows, excellent debugging skills.
• Maintain and update technology collaterals

Preferred Experience

• Experience in ASIC Physical Design and/or CAD development with industry experience in STA, constraints, timing signoff and physical design
• Hands-on experience with Place and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, Innovus, Primetime, Primeshield, PT-PX, Formality, Conformal, RedHawk, etc.
• Experience in 5nm and below technologies
• Experience with Python and Perl.
• Knowledge and Experience in ML and LLM
• Experience with data analytics applications, database management
• Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
• Experience with physical design is a plus.
• Has Synthesis or physical implement experience.
• Experience with lower power design methodology.
• Good English skills on talking, presentation and writing documents.
• Good communication and strong sense of responsibility, task scheduling, and time management.

LOCATION:

Santa Clara, California

DDR Training Architecture and Post-silicon Validation

As a member of the CT Server DDR team, we are looking for an experience DDR PHY engineer who can be responsible for DDR training architecture and PHY post-silicon validation.

The Person

The engineer needs to be hands-on in defining DDR training algorithms and validating them. The engineer needs to work with design and FW teams on the specification of the algorithms and their implementation

Key Responsiblities

• Run system simulations and correlate with silicon results
• Able to process post-silicon validation data and drive the next steps
• Support cross-functional teams with PHY implementation details

Preferred Experience

• Strong coding skills in C, Matlab, System Verilog and Python preferred
• Signal integrity (SI) and power integrity (PI) knowledge

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Santa Clara, CA ( Open to other AMD locations )

Hardware Product Application Engineer

HW Product Application Engineer will work closely with customers to develop servers using AMD server CPUs by providing platform or HW related support. Those includes delivering necessary trainings, answering any inquires, creating collaterals, reviewing design files, and debugging issues, working with internal teams.

The Person

The candidate must be highly motivated, innovative, and be able to work in a fast-paced environment. The candidate must be able to quickly analyze different customer scenarios to come up with the best approach to tackle tough problems. The successful candidate will have strong analytical skills and debug methodology, strong communication skills, be self-motivated, and have a desire to help customers solve problems.

Key Responsibilities

• Directly work with customers to enable successful deployment of AMD server platforms
• Provide customers technical training on AMD based platforms.
• Perform platform reviews (block-level, schematic, and layout review) of customer designs.
• Engage directly on key technical topics, issues, architecture discussions, and performance optimizations
• Own and drive closure to issues reported by customer on HW and platform domain which includes
• Attend regular customer calls and answer HW, platform and silicon related questions.
• Perform first level triage and debug for customer reported issue.
• Participate in joint debug at customer site as needed.
• Develop and present customer communications for silicon and platform issues. Co-develop technical collateral, such as application note, user guide, sample, and reference design materials
• Engage directly on key technical topics, issues, architecture discussions, and performance optimizations with customers and internal teams
• Collaborate seamlessly across domains including platform and silicon engineering, product management, and field application engineering

Preferred Experience

• 10+ years / Proven track record of success working directly with customers to develop systems from concept to production.
• Strong knowledge in x86 processors, DDR5/6, CXL, PCIe, SATA, USB, multiprocessor systems, power management and system management.
• Experience in the following area is highly preferred.
  • Hands-on lab works
  • HW related issue debug on server platform
  • Server motherboard design
  • High-speed IO board design and/or signal integrity validation.
• Experience in the following area is plus.
  • Power delivery design.
  • CPU performance turning
  • Team player with passion and a keen sense of urgency and strong drive
• Team player with passion and a keen sense of urgency and strong drive

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in electrical or computer engineering

LOCATION:

• Santa Clara, CA