Broadcom Top Jobs 🔥 Apply Now 👆 before its expired

Broadcom is focused on technology leadership and category-leading semiconductor and infrastructure software solutions. The company is a global leader in numerous product segments serving the world’s most successful companies.

Package Design Engineer

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.  You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations.  These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more.  You’ll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.

 

RESPONSIBILITIES:

·        Overall design responsibility for ASIC package designs and layout, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.

·        2 or more years experience with Cadence APD, SiP, or equivalent package layout CAD tool (3 or more years is preferred)

·        Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.

·        Schedule, prioritize, & track your work across 2+ projects simultaneously

·        General flip-chip BGA package design & engineering

·        Project management and customer interface for your design projects

·        Contribute to efficiency improvements for the design group

EDUCATION/EXPERIENCE & REQUIREMENTS:

·        BSEE or similar field  and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes

·        Knowledge of package-level signal integrity and power integrity, to apply to package designs

·        Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.

·        Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers

·        Self-management and organization skills

 

 

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $107,000 – $190,000.

 

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

 

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

R&D Software Engineer – VCF Networking

The VCF networking management stack is responsible for configuration of core network virtualization technology used in all of Broadcom’s VMware Cloud Foundation (VCF) Division products. You will have the opportunity to work on bleeding edge network virtualization technologies, network overlays and layer-2 switching.

The VCF Division works to build products and solutions that power the hybrid cloud.  Working alongside other highly motivated and capable engineers you will get to interact with our largest customers to define the next generation of Broadcom’s industry-leading VMWare Cloud Foundation platform

 

Job duties include :

  • Design and develop a large scale distributed configuration management system.
  • Work closely with Product Management and cross-functional teams to analyze information and user needs to determine and develop software solutions working on moderately complex problems of diverse scope.
  • Apply company policies and procedures to resolve a wide range of technical and programming issues in creative ways
  • Develop and direct software systems testing and validation procedures, programming, and documentation

 

Requirements:

  • Masters or Bachelors in Computer Science
  • Bachelors and 12+ years of related experience; at this level a postgraduate degree is typically expected or Masters degree and 10+ years of related experience or PhD and 7+ years of related experience
  • Experience in distributed systems and handling of large-scale enterprise systems
  • Experience in networking stack. Knowledge of cloud computing and virtualization is a plus
  • Knowledge of cloud computing/virtualization is a plus
  • Proficient in Java and Python. Knowledge of C++ is a plus.

If you are someone who embraces new technology, enjoys continuous learning, and desires a collaborative work environment, we encourage you to explore this opportunity with Broadcom.

 

Additional Job Description:

The annual base salary range for this position is $141,000 – $225,000.

ASIC Automation and Integration Engineer

Would you like to conceive and develop leadership silicon technology for leading AI/ML and cloud operators?  Come join the team creating technology that fuels the next generation AI/ML networks, mobile content, and cloud mega data centers!

 

The candidate will work on leading edge products in the area of Ethernet/IP switching for multi-scale data centers. We are looking for engineers that want to create flows & support synthesis / timing for new designs that can evolve rapidly over the next several generations in a very dynamic market.

 

This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products.

 

All aspects of front end design will be involved, with strong emphasis on flow development & synthesis/timing.

BSEE and 8+ years of industry experience in flow development , synthesis constraints development / STA is a must, or MSEE and 6+ years of industry experience. A strong design background is preferred & the candidate should have a strong scripting/automation experience using Python / Perl

Must have strong communication and documentation skills.  Must be a self-starter and a strong team player.

Candidates will primarily be responsible for working on automating design flows, supporting synthesis deliverables & STA. Apart from this, the candidate is also expected to handle minimal design work to support certain shared modules that will help the team focus on real design issues taking focus off of day-to-day repetitive jobs.

 

Additional Job Description:

Compensation and Benefits

 

The annual base salary range for this position is $107,000 – $171,000

Package Design Engineer

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.  You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations.  These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more.  You’ll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.

 

RESPONSIBILITIES:

·        Overall design responsibility for ASIC package designs and layout, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.

·        2 or more years experience with Cadence APD, SiP, or equivalent package layout CAD tool (3 or more years is preferred)

·        Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.

·        Schedule, prioritize, & track your work across 2+ projects simultaneously

·        General flip-chip BGA package design & engineering

·        Project management and customer interface for your design projects

·        Contribute to efficiency improvements for the design group

EDUCATION/EXPERIENCE & REQUIREMENTS:

·        BSEE or similar field  and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes

·        Knowledge of package-level signal integrity and power integrity, to apply to package designs

·        Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.

·        Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers

·        Self-management and organization skills

 

 

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $107,000 – $190,000.

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Updated: March 31, 2025 — 9:21 am

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