• Develop and implement DFT strategies for mixed-signal ICs, considering factors such as fault coverage, test time, and in-system test.

• Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns.

• Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement.

• Generate high-quality test patterns using automated test pattern generation (ATPG) tools.

• Verify the correctness of DFT implementation through simulation and hardware testing.

• Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process.

• Bachelor’s degree in Electrical Engineering or Computer Engineering.

• 10+ years of experience in DFT for mixed-signal ICs.

• Understanding of DFT concepts, including scan insertion, BIST, and boundary scan.

• In-depth knowledge of DFT EDA tools (Siemens/Synopsys).

• Familiarity with IEEE standards 1149, 1500, and 1687.

• Experience with fault simulation and coverage analysis tools.

• Problem-solving and analytical skills.

• Strong communication skills

• Work independently and as part of a team.

• Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation.

• Master’s degree in Electrical Engineering or Computer Engineering.

• Experience with mixed-signal DFT methodologies.

• Knowledge of scripting languages (e.g., Perl, Python) for automation.

ASIC Engineer – Infra Specialist

Preferred Qualifications

• Demonstrated expertise in developing with RTOS (preferably Zephyr) and embedded Linux

• Experience in peripheral drivers like PCIe, UART, I2C, SPI is plus

• Experience in Python or any other scripting language for tooling, test automation is a plus

• Experience leading complex features or projects across multiple teams

• Experience with lab instrumentation such as oscilloscopes, logic/protocol analyzers for debugging embedded systems at hardware level

• Experience delivering end to end product solution

Demonstrated expertise in one or several of the following areas – SoC block understanding, board bring-up

India Corporate Tax Manager

This role will report to the APAC Head of Tax along with working closely and supporting another India Tax Manager. As a member of the Asia Pacific Tax team located in Gurgaon, this role will be part of the wider team in managing all the India direct tax compliances including supporting year-end close activities with local accounting and global tax accounting teams, supporting tax corporate tax audits, driving tax initiatives/processes to bring in additional efficiencies. This role will partner with the various functions (Legal, Accounting, Indirect Tax and other cross functional teams) and provide quality tax support. The role also involves significant interaction with the broader global tax group in Singapore and Menlo Park. This is a full time in-office role based in Gurgaon.

India Corporate Tax Manager Responsibilities

• Work closely with the India Tax Manager to support, coordinate and manage the tax positions of the India legal entities in compliance with legislation and corporate guidelines and to safeguard the Company from financial risks and claims.

• Support the wider team in the corporate tax compliances and reporting requirements for India – including Corporate tax returns, Withholding Tax compliance process, tax payment calculations, tax forecasts, and deferred tax calculations, and technical analysis in support of audit issues. Will also include oversight and co-ordination of compliance activities outsourced to external service providers.

• Assist and manage the direct tax audits and controversy matters in India.

• Manage the other compliances like the quarterly computation and payment of advance taxes, applicable TDS on inter-company payments etc.

• Work with the global tax team to implement strategic goals, tax initiatives and policies.

• Establish a strong relationship with the India businesses, finance, legal and policy leaders to share tax views and information.

• Review Transfer Pricing Reports as prepared by the external service provider and ensure transfer pricing obligations are fulfilled under local transfer pricings laws and regulations.

• Support and assist with the quarterly tax accounting and reporting. This includes the calculation and tracking of quarterly / year-end transfer pricing corrections, direct tax exposures and Uncertain Tax Positions.

Minimum Qualifications

• Bachelor’s degree in Accounting or Law.

• A minimum of 8 years of relevant tax experience.

• Broad tax experience including tax advisory, transfer pricing, tax compliance and tax controversy.

• Experience in tax audit management in India.

• Strong project management skills, strong analytical, organization, documentation, and research skills.

Preferred Qualifications

• Prior experience with Law Firm/Big 4 accounting firm is preferred.

• Prior experience with corporate tax responsibilities for a large multinational company is preferred.

• Strong communication skills and ability to simplify and communicate complex business/ tax information.

• Ability to work as a team and interact with personnel at all levels of the organization.

• Hands-on, independent, able to multi-task and prioritize.

• Highly organized, meticulous, and ability to work independently in a high pressure, fast-paced environment.

Proficient with Excel and Word.

ASIC Engineer, Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Engineer, Design Verification Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

• Develop functional tests based on verification test plan

• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

• Debug, root-cause and resolve functional failures in the design, partnering with the Design team

• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications

• Track record of ‘first-pass success’ in ASIC development cycles

• Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

• 14+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification

• 14+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies

• Experience in one or more of the following areas along with functional verification – SV Assertions, Formal, Emulation

• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications

• Experience in development of UVM based verification environments from scratch

• Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs

• Experience with revision control systems like Mercurial(Hg), Git or SVN

• Experience with verification of ARM/RISC-V based sub-systems or SoCs

• Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet

Experience working across and building relationships with cross-functional design, model and emulation teams