Senior STA Engineer

Responsibilities:

§ Hands on responsibility in top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc).

§ Work with a team of engineers on timing closure and constraints generation/debug.

§ Has prior STA & timing closure experience.

§ Understanding of different implementation styles of clock in design and latency/skew.

§ Understanding of clock domain crossings, source synchronous buses, multi-voltage timing.

§ Understanding of timing sign off flow and methodology, timing budgeting, derating and timing across different voltage domains § Working knowledge of special timing checks (Asynchronous, source sync interfaces, etc).

§ Interact with RTL and SOC physical implementation teams to resolve timing issues.

§ Mentoring junior engineers in different areas of timing flows and methodologies § Ability to influence flow and methodology enhancements for improvement § Ability to work independently and influence cross functional teams to make good technical design trade-offs between power, area, timing Skills and Qualifications

Background/Experience:

o 8+ years relevant experience preferred

o Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must

o Understanding and working knowledge of the SOC/ASIC design flow.

o Possesses strong technical qualities and skillsets with good analytical debug skills

o Experience with smaller process nodes is strongly preferred

o Working knowledge and detail understanding of OCV, AOCV & POCV is preferred.

o Strong hands-on experience with industry standard STA tools (Ex. PrimeTime, Tempus)

o Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools an added plus

o Experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs is a plus.

o Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage.

o Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is preferred.Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to details.

Senior SOC Physical Design Engineers

Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips

by means of Synthesis , Place and Route, STA , timing and physical signoffs

– Hands on experience doing physical design and timing closure of complex blocks and full-chip designs

– Should have strong understanding of timing, power and area trade-offs and optimization of PPA

– Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities

– Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows

– Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .

– Expertise in block level and full-chip SDC cleanup, Synthesis optimization , Low Power checking and logic equivalence checking

– Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling)

– Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.

– Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence

– Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning,

high speed signal and clock planning and feed-through planning is a plus

– Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level

– Should have gone through 4+ recent successful SoC tape-outs

– Should have 8 ~ 14 years of experience in physical implemenation and design

Senior Director, Data Science,Machine Learning & AI

SEA India Team is currently operating in Chennai, recruiting world-class engineers who share our “Innovation through Passion” philosophy and thrive in a fast-paced, cross-team, results-driven environment, with a focus on highly visible, challenging, and cross-discipline projects. We have been growing exponentially year on year in terms of revenue, size and achievements.

Role and Responsibilities:

• Create and maintain optimal data pipeline architecture
• Build the infrastructure required for optimal data extraction, transformation, and loading of data from a wide variety of sources using big data technologies
• Assemble large, complex data sets that meet functional/non-functional business requirements
• Identify/design/implement internal process improvements, automating manual processes, optimizing data delivery, re-designing infrastructure for greater scalability, etc.
• Build analytics tools that utilize the data pipeline to provide actionable insights to business
• Maintain security and data privacy in an environment secured using Kerberos and LDAP
• Build test prototypes for the functional/technical problems identified
• Propose ETL best practices/standards
• Work with stakeholders including the Executive, Product, Data and Design teams to assist with data-related technical issues and support their data infrastructure needs
• Work with cross-functional teams in a dynamic environment

Skills and Qualifications:

• 4+ years of experience in big data tools: Hadoop, hive, Spark, Kafka, HBase, Flume, Pig, KUDU etc.
• 4+ years of experience in programming languages: Python/Java/Scala, etc. Fluency in writing shell scripts [bash, korn]
• Experience with working in Linux based environment
• Expertise in ETL tools and Business Intelligence (BI Tools)
• Experience/expertise in Snowflake or Informatica/ Teradata / Tableau, DWH.
• Experience with relational SQL and any NoSQL databases
• Basic understanding of AWS cloud services: EC2, EMR, RDS
• Experience with stream-processing systems: Storm, Spark-Streaming, etc.
• Strong ability in building complex analytical queries on various relational databases
• Experience in building and optimizing data pipelines, architectures and data sets
• Analytical and problem-solving skills applied to the Big Data domain
• Experience in performing root cause analysis on internal/external data and processes to answer specific business questions and identify opportunities for improvement
• Strong analytic skills related to semi/unstructured datasets
• Experience in manipulating, processing and extracting metrics from large disconnected datasets

Graphics Driver Development – GPU – Linux / Android Stack

Position Summary

Samsung is a world leader in Memory, LCD and System LSI technologies. We are currently looking for exceptional software and hardware talent to join our Samsung Indian Design Centre and our Advanced Computing Lab (ACL) in San Jose, CA. SARC was established in Austin, TX in 2010 to be one of Samsung’s strategic investments in high performance low power ARM based device technology. Presently our GPU design teams, located in Austin (SARC) and San Jose (ACL) & India Bangalore are developing a GPU that will be deployed in Samsung mobile products. Our System IP team is working on Coherent Interconnect and memory controller architectures.

As a GPU Engineer , you will work as part of a team actively working to design and document major units in a GPU pipeline targeted at Mobile graphics applications and potentially other related markets. This is a mid to senior level position where the candidate will be in an individual contributor role, tasked with driving the functional and cycle simulators for GPU pipeline and working with cross functional teams including RTL design, modeling and software on various sub-blocks of the end solution.

Role and Responsibilities

Design and document major units in a GPU pipeline targeted at Mobile graphics and machine learning

Develop functional and cycle simulators for GPU pipeline. Collect statistics to evaluate potential benefit of optimizations, prototype to test functional correctness and specify the scheme in detail for next level of implementation in hardware and or software

Collaborate with implementation, modeling, and software teams to define and develop microarchitecture, software implementation, and/or a verification plan

Investigate alternate approaches for important GPU workloads, incremental optimizations, and rebalancing to maximize performance in future key workloads

Work with software developers to understand important trends in future graphics and AI applications, problems faced by application and middleware developers

Find and/or implement applications to exercise novel algorithms in drivers/hardware

Minimum requirements: 3 to 18 Years

Experience using parallel programming

Knowledgeable in GPU or other parallel processing architectures.

Strong knowledge of GPU architecture mainly on Linux Stack or Kernel Mode Driver

Knowledge of key mobile GPU graphics workloads and compute application workloads such as computer vision, image processing, AI and Image compression

Knowledge of game applications, game rendering engines, academic papers on advanced rendering techniques desirable

Expertise in implementing advanced graphics rendering techniques, machine-learning (AI) approaches

Proven ability to debug complex issues in multi-threaded environments

Understanding of Operating System fundamentals and concepts

Familiarity with offline and JIT compiler designs

Background in Linux and Android development

Strong C, C++ and Python programming experience of industrial experience in systems programming (driver development a strong plus)

Strong algorithmic background and outstanding problem-solving skills

System level performance analysis and strong OS fundamentals (memory management, multithreading/synchronization, user/kernel mode interaction)

Excellent C and C++ programming skills (assembly a plus)

Understanding of rasterization pipeline and modern GPU architectures

Excellent communication and teamwork skills

Ability to own a problem and drive it to completion

Preferred candidate will possess the following:

Experience working with ARM 64-bit architecture

Experience developing system software for Android OS

Knowledge of high-level shading languages, e.g., GLSL/HLSL

Understanding of modern real-time rendering game engines